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aS2-Quadrant Multiplying 8-Bit DACs * 8 Independent at * Dual Positive (+10 V and +5 V) Supplies or D Dual.(+5 V) Supplies Capability * High Speed: w Rate w - 12.5 MHz Digital ClockTime: 150ns to 8-bit V Settling -V w (typ)
FEATURES
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MP7641
8-Channel Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Port
* DACs Matched to +0.5% (typ) * Chip Select Available: MP7651 * Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz * VREF/2 Output Preset Level * Latch-Up Free * ESD Protection: 2000 V Minimum
* * * *
Voltage Reference Input Bandwidth: 10 MHz Low Power: 150mW Low AC Voltage Reference Feedthrough Excellent Channel-to-Channel Isolation DNL = +0.8 LSB, INL = +1 LSB (typ)
-
APPLICATIONS
* Direct High-Frequency Automatic Gain Control * Video AGC & CCD Level AGC * Convergence Adjustment for High-Resolution Monitors (Workstations)
GENERAL DESCRIPTION
The MP7641 is ideal for direct gain control of video, composite video, CCD and other high frequency analog signals. The device includes 8-channels of high speed, high bandwidth, two quadrant multiplying, 8-bit accurate digital-to-analog converter. It includes an output drive buffer per channel capable of driving a +1mA (typ) to a load. DNL of better than +0.8 LSB is achieved with a channel-to-channel matching of better than 0.5% (typ). Stability, matching, and precision of the DACs are achieved by using EXAR's thin film technology. Also, excellent channel-tochannel isolation is achieved with EXAR's BiCMOS process which cannot be achieved using a typical CMOS technology. An open loop architecture (patent pending) provides wide small signal bandwidth from VREF to output up to 10 MHz (typ),
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fast output settling time, and VREF feedthrough isolation of -65dB or better. In addition, low distortion in the order of 0.25% with a 1 V p-p, 1 MHz signal is achieved. The combination of a constant input Z and the ability to vary AGND within +300 mV allows flexibility for optimum system design. The MP7641 has a serial data 3-wire standard -processor logic interface to reduce pin count, package size, and board wire (space). The MP7641 is fabricated on a junction isolated, high speed BiCMOS (BiCMOS IVTM) process with thin film resistors. This process enables precision high speed analog/digital (mixedmode) circuits to be fabricated on the same chip.
Rev. 2.00 1
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MP7641
SIMPLIFIED BLOCK DIAGRAM(c)
VDD VCC
RST 8 8-Bit Latch DAC 0 +1
VR0 VO0 VR1 8 8-Bit Latch DAC 1 +1 VO1
VR7 8 8-Bit Latch DAC 7 +1 VO7
8 8 8 LD CLK 1-Bit Latch 1-Bit Latch 4-8 DEC 4 DB0 to DB7 4-Bit Address SDO 12-Bit Shift Register 3-State Buffer SDI LD
VEE
DGND
AGND
ORDERING INFORMATION
Package Type
SOIC Plastic Dip
Temperature Range
-40 to +85C -40 to +85C
Part No.
MP7641AS MP7641AN
INL (LSB)
+1 +1
DNL (LSB)
+0.8 +0.8
Gain Error (% FSR)
+1.5 +1.5
Rev. 2.00 2
MP7641
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
VO1 VO2 VR2 VR3 VO3 VDD VCC VEE AGND DGND VO4 VR4 VR5 VO5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VR1 VR0 VO0 AGND RST LD CLK SDO SDI AGND VO7 VR7 VR6 VO6
VO1 VO2 VR2 VR3 VO3 VDD VCC VEE AGND DGND VO4 VR4 VR5 VO5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VR1 VR0 VO0 AGND RST LD CLK SDO SDI AGND VO7 VR7 VR6 VO6
28 Pin PDIP (0.300") NN28
28 Pin SOIC (EIAJ, 0.335") R28
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NAME VO1 VO2 VR2 VR3 VO3 VDD VCC VEE AGND DGND VO4 VR4 VR5 VO5 VO6
DESCRIPTION DAC 1 Output DAC 2 Output DAC 2 Reference Input DAC 3 Reference Input DAC 3 Output Digital Positive Supply Analog Positive Supply Analog Negative Supply Analog Ground Digital Ground DAC 4 Output DAC 4 Reference Input DAC 5 Reference Input DAC 5 Output DAC 6 Output
PIN NO. 16 17 18 19 20 21 22 23 24 25 26 27 28
NAME VR6 VR7 VO7 AGND SDI SDO CLK LD RST AGND VO0 VR0 VR1
DESCRIPTION DAC 6 Reference Input DAC 7 Reference Input DAC 7 Output Analog Ground Serial Data/Address Input Serial Data Output Shift Register Clock Load Signal; Load Data to Selected DACs Reset Signal; Reset all DACs to VREF/2 Analog Ground DAC 0 Output DAC 0 Reference Input DAC 1 Reference Input
Rev. 2.00 3
MP7641
ELECTRICAL CHARACTERISTICS TABLE FOR DUAL SUPPLIES
Unless Otherwise Noted: VDD = 5 V, VCC = +5 V, VEE = -5 V, VREF = 3 V and -3 V, T = 25C, Output Load = Open, AGND=DGND=0 V
25C Typ Tmin to Tmax Min Max
Parameter DC CHARACTERISTICS Resolution (All Grades) Differential Non-Linearity Integral Non-Linearity Monotonicity Gain Error Zero Scale Offset Output Drive Capability REFERENCE INPUTS Impedance of VREF Voltage Range DYNAMIC CHARACTERISTICS2 Input to Output Bandwidth Input to Output Settling Time5 Small Signal Voltage Reference Input to Output Bandwidth Small Signal Voltage Reference Input to Output Bandwidth Voltage Settling from VREF to VDAC Out Voltage Settling from Digital Code to VDAC Out VREF Feedthrough Group Delay Harmonic Distortion Channel-to-Channel Crosstalk Digital Feedthrough Power Supply Rejection Ratio POWER CONSUMPTION Positive Supply Current Negative Supply Current Power Dissipation DIGITAL INPUT CHACTERISTICS Logic High3 Logic Low3 Input Current Input Capacitance2
Symbol
Min
Max
Units
Test Conditions/Comments
N DNL INL GE ZOFS IO
8 +0.8 +1 Guaranteed +20 +1 +1.5 +75
8 +1 +1 Guaranteed +1.5 +75
Bits LSB LSB % FSR mV mA FSR = Full Scale Range1
REF VR
6 VEE +1.5
12 18 VCC -1.8
6
18 V
k VREF
Max Swing is AGND +3 V
RL = 5 k, CL = 20 pF 10 150 10 5 8 275 275 -65 20 0.5 -75 1 0.02 300 300 325 325 MHz ns MHz MHz ns ns dB ns % dB nVS %/% VR = 1.6 V p-p, RL = 5k to VEE VR = 1.6 V p-p, RL = 5k to VEE VOUT=50mV p-p above code 16 VOUT=50mV p-p for all codes VR=0 to VR = 3V Step6 to 1 LSB ZS to FS to 1 LSB Codes=0 @ 1 MHz VREF=1MHz Sine 3V p-p @ 1 MHz, single channel CLK to VOUT V=+5%
tr tr tsr tsd FDT GD THD CT Q PSRR
ICC IEE PDISS
15 15 150
25 25 250
30 30 300
mA mA mW
VREF = 0 V VREF = 0 V VREF = 0 V, Codes = all 1
VIH VIL IL CL
2.4 0.8 +10 8
2.4 0.8 +10 8
V V A pF
Rev. 2.00 4
MP7641
ELECTRICAL CHARACTERISTICS TABLE
Description DIGITAL TIMING SPECIFICATIONS2, 4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Reset Pulse Width Clock Edge to Load Rising Edge Clock Edge to Load Falling Edge Load Falling Edge to SDO 3-state Enable Load Rising Edge to SDO 3-state Disable Load Falling Edge to CLK Disable Load Rising Edge to CLK Enable LD Set-up Time with Respect to CLK tCH, tCL tDS tDH tPD tLD tRST tCKLD1 tCKLD2 tHZ1 tHZ2 tLDCK1 tLDCK2 tLDSU 40 10 15 40 100 50 100 0 50 35 25 35 15 100 60 100 0 60 50 40 50 20 50 10 15 50 ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Conditions
NOTES Full Scale Range (FSR) is 3V. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See Figures 2 and 3. 5 For reference input pulse: tR = tF > 100 ns.
1
Specifications are subject to change without notice
Rev. 2.00 5
MP7641
ELECTRICAL CHARACTERISTICS TABLE FOR DUAL POSITIVE SUPPLIES
Unless Otherwise Noted: VDD = 5 V, VCC = 10 V, VEE = 0 V, VREF = 3 V and -3 V, T = 25C, Output Load = Open, AGND = (VCC + VEE)/2 = 5 V, DGND = 0 V
Parameter DC CHARACTERISTICS Resolution (All Grades) Differential Non-Linearity Integral Non-Linearity Monotonicity Gain Error Zero Scale Offset Output Drive Capability REFERENCE INPUTS Impedance of VREF Voltage Range DYNAMIC CHARACTERISTICS2 Input to Output Bandwidth Input to Output Settling Time5 Small Signal Voltage Reference Input to Output Bandwidth Small Signal Voltage Reference Input to Output Bandwidth Voltage Settling from VREF to VDAC Out Voltage Settling from Digital Code to VDAC Out VREF Feedthrough Group Delay Harmonic Distortion Channel-to-Channel Crosstalk Digital Feedthrough Power Supply Rejection Ratio POWER CONSUMPTION Positive Supply Current Negative Supply Current Power Dissipation DIGITAL INPUT CHACTERISTICS Logic High3 Logic Low3 Input Current Input Capacitance2 VIH VIL IL CL 2.4 0.8 +10 8 2.4 0.8 +10 8 V V A pF ICC IEE PDISS 15 15 150 25 25 250 30 30 300 mA mA mW VREF = 0 V VREF = 0 V VREF = 0 V, Codes = all 1 10 150 10 5 8 275 275 -65 20 0.5 -75 1 0.02 300 300 325 325 MHz ns MHz MHz ns ns dB ns % dB nVS %/% REF VR 6 12 18 VEE +1.5 VCC -1.8 6 18 V k VREF N DNL INL GE ZOFS IO +20 +1 8 +0.8 +1 Guaranteed +1.5 +75 8 +1 +1 Guaranteed +1.5 +75 Bits LSB LSB % FSR mV mA FSR = Full Scale Range1 Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
Max Swing is AGND +3 V
RL = 5 k, CL = 20 pF VR = 1.6 V p-p, RL = 5k to VEE VR = 1.6 V p-p, RL = 5k to VEE VOUT=50mV p-p above code 16 VOUT=50mV p-p for all codes VR=0 to VR = 3V Step6 to 1 LSB ZS to FS to 1 LSB Codes=0 @ 1 MHz VREF=1MHz Sine 3V p-p @ 1 MHz, single channel CLK to VOUT V=+5%
tr tr tsr tsd FDT GD THD CT Q PSRR
Rev. 2.00 6
MP7641
ELECTRICAL CHARACTERISTICS TABLE
Description DIGITAL TIMING SPECIFICATIONS2, 4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Reset Pulse Width Clock Edge to Load Rising Edge Clock Edge to Load Falling Edge Load Falling Edge to SDO 3-state Enable Load Rising Edge to SDO 3-state Disable Load Falling Edge to CLK Disable Load Rising Edge to CLK Enable LD Set-up Time with Respect to CLK tCH, tCL tDS tDH tPD tLD tRST tCKLD1 tCKLD2 tHZ1 tHZ2 tLDCK1 tLDCK2 tLDSU 40 10 15 40 100 50 100 0 50 35 25 35 15 100 60 100 0 60 50 40 50 20 50 10 15 50 ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Conditions
NOTES 1 Full Scale Range (FSR) is 3V. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See Figures 2 and 3. 5 For reference input pulse: tR = tF > 100 ns. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1,2
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6.5 V VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0 V VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6.5 V VRi to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to VEE VOi to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to VEE Digital Input & Output Voltage to DGND -0.5 to VDD +0.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . -65C to 150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C Package Power Dissipation Rating @ 75C PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . . 6mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s.
APPLICATIONS INFORMATION Refer to Section 8 for Applications Information
Rev. 2.00 7
MP7641
SDI 1 (Data In) 0 CLK LD 1 0 1 0 DAC Register Loaded A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
VOUT
Figure 1. Serial Data Timing and Loading
tDS SDI 1 0 SDO 1 0 1 CLK 0 tCL tCH tPD tCKLD2 tCKLD1 tLDSU tLDCK1 tLDCK2 tDH tHZ1 tHZ2 HIGH Z
1 LD 0 VOUT
tLD tSD + 1/2 LSB BAND
Figure 2. Detail Serial Data Input Timing (RST = "1")
RST
1 0
tRST
tSD VO = VREF VO = VREF/2 + 1/2 LSB ERROR BAND
Figure 3. RESET Operation
Rev. 2.00 8
MP7641
THEORY OF OPERATION
The MP7641 is equipped with a serial data 3-wire standard -processor logic interface to reduce pin count, package size, and board wire (space). This interface consists of LD which controls the transfer of data to the selected DAC channel, SDI (serial data/address input), CLK (shift register clock) and SDO (serial data output). When the LD signal is high, CLK signal loads the digital input bits (SDI) into the 12-bit shift register (4 bits address A3 to A0, then 8 bits data D7 to D0). The LD signal going low loads this data into the selected DAC. The LD signal going low Function
Shift Data In and Out Stop Shifting Data In and Out Load DACs DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 No Operation 10 10 10 10 10 10 10 10 No Operation No Operation No Operation X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 X X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
also disables the serial data input (SDI), output (SDO 3-stated) and the CLK input. This design tremendously reduces digital noise, and glitch transients into the DACs due to free running CLK and SDI. Also, 3-stating the SDO output with LD signal would allow read back of pre-stored digital data of the selected package using one SDO wire for all DAC ICs on the board. Note also that the reset signal (RST) resets all analog outputs to 1/2 of VREF, regardless of any digital inputs. Note that the input VRi is referenced to AGND. CLK
01 Repeat X
A3 A2 A1 A0
X X X X X X X X
LD
1 0
RST
1 1
SDI
Data Input Valid X
SDO
Data Output Valid Hi-Z
1 1 Reset all DACs to X VREF/2
1 1 X
1 1 X
0 1 X
1 1 0
X X X
Hi-Z Hi-Z X
Table 1. Digital Function Truth Table Serial In/Serial Out
DB7 DB6 MSB
0 0 0 0
DB5
DB4
DB3
DB2
DB1
DB0 DAC Output Voltage D LSB VOi = AGND + (VRi - AGND) ( 256 )
0 1 AGND 1 (VRi - AGND) ( 256 ) + AGND
0 0
0 0
0 0
0 0
0 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
254 (VRi - AGND) ( 256 ) + AGND 255 (VRi - AGND) ( 256 ) + AGND
Table 2. DAC Transfer Function Analog Output vs. Digital Code
Rev. 2.00 9
MP7641
OPERATION WITH DUAL POSITIVE POWER SUPPLIES
For the dual positive supplies operation, VCC = +10 V, VDD = 5 V, VEE = 0 V and analog output zero level is to be referenced to (VCC + VEE) /2 by setting the AGND pin to 5 V.
MICROPROCESSOR INTERFACE
ADDRESS BUS A0 to A23
AS VMA
CS
ADDRESS DECODER
MC68000
UPA 1/4 7HC125 UDS DB0 DB0 to DB15 16 FROM SYSTEM RESET 16 DATA BUS CLK LD SDI MP7641 RST
Figure 4. MC68000 Interface (Simplified Diagram)
A0 to A15
16 3 E1 A0 to A2 74LS138 ADDRESS DECODER
1
ADDRESS BUS
MC6800
02 R/W 8 E3 E2
DB0 to DB7
8 DATA BUS
DB7
LD SDI
CLK MP7641 RST
FROM SYSTEM RESET NOTES: 1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each WRITE presents the next bit 2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE location 2000, R/W, and 02. A WRITE to address 4000 transfers data from the input shift register to the DAC register.
Figure 5. MC6800 Interface (Simplified Diagram)
Rev. 2.00 10
MP7641
8
ADDRESS BUS 8 3 A0 to A2 74LS138 E3 ADDRESS DECODER
8085
ALE
8212
+5
E1
WR
E2
8
DATA BUS
SOD LD SDI CLK MP7641 RST
FROM SYSTEM RESET
Figure 6. 8085 Interface (Simplified Diagram)
NOTES: 1. Clock generated by WR and decoding address 8000 2. Data is clocked into the DAC shift register by executing memory write instructions. the clock input is generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction to address 4000. 3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Rev. 2.00 11
MP7641
VRI1 8 8 VOI1 VRI2 8 8 VOI2 VRIN 8 8 VOIN
IC (1)
IC (2)
MP7641 SDI LD SDO
IC (n)
MP7641 SDI LD SDO
PC
MP7641 SDI LD SDO
DATA LD CLK
Figure 7. Simplified Diagram Configuration A
VRI1 8
VOI1 8
VRI2 8
VOI2 8
VRIN 8
VOIN 8
IC (1)
MP7641
IC (2)
MP7641 SDI LD SDO
IC (n)
MP7641 SDI LD SDO
PC
DATA OUT DATA n CS OR LD CLK
SDI LD
SDO
#1
#2
#n
Figure 8. Simplified Diagram Configuration B
Rev. 2.00 12
MP7641
VRI1 VOI1 VRI2 VOI2 VRIm VOIm
1 SDO ADDRESS n 2
IC (1)
MP7641 2n SDI LD SDO
IC (2)
MP7641 SDI LD SDO2
IC (m)
MP7641 SDI LD SDOm
PC
WR (SDI) DATA IN CLK
Figure 9. Simplified Diagram Configuration C
MP7641 EVALUATION BOARD
Measurement Buffer 1.6 V p-p 5 pF 1k Test Load 27 28 3 4 12 13 16 17 26 1 2 5 11 14 15 18 5k
VR0 VO0 VR1 VO1 VR2 VO2 VR3 VO3 VR4 VO4 VR5 VO5 VR6 VO6 VR7 VO7
20 pF
VOUT
9
DGND AGND
10
MP7641
All resistors = 50 unless otherwise specified Gain of all DACs set to 1 (no attenuation) NOTE: See Graphs 1 through 8
Figure 10. Single Channel Crosstalk
Rev. 2.00 13
MP7641
5 pF 1.6 Vp-p Test Load 27 28 3 4 12 13 16 17 26 1 2 5 11 14 15 18 19 20 21 22 23 24 25 10 1k
VR0 VO0 VR1 VO1 VR2 VO2 VR3 VO3 VR4 VO4 VR5 VO5 VR6 VO6 VR7 VO7 N/C SDI SDO CLK LD RST N/C
20 pF
5k
VOUT
9
DGND AGND
MP7641
All resistors = 50 unless otherwise specified. Gain of all DACs set to 1 (no attenuation). NOTE: See Graph 20B.
Figure 11. All Hostile Crosstalk
5 pF 1.6 Vp-p 1k Test Load 27 28 3 4 12 13 16 17 26 1 2 5 11 14 15 18 19 20 21 22 23 24 25 10
VR0 VO0 VR1 VO1 VR2 VO2 VR3 VO3 VR4 VO4 VR5 VO5 VR6 VO6 VR7 VO7 N/C SDI SDO CLK LD RST N/C
20 pF
5k
VOUT
9
DGND AGND
MP7641 All resistors = 50 unless otherwise specified. Gain of all DACs set to 1 (no attenuation) except monitored DAC set to 0 (full attenuation). NOTE: See Graph 20A.
Figure 12. All Hostile Crosstalk & Feedthrough
Rev. 2.00 14
MP7641
5 pF
VCC
VEE
1k Test Load
DUT
27 28 3 4 12 13 16 17 VR0 VO0 VR1 VO1 VR2 VO2 VR3 VO3 VR4 VO4 VR5 VO5 VR6 VO6 VR7 VO7 N/C SDI SDO CLK LD RST N/C 9 DGND AGND 26 1 2 5 11 14 15 18 19 20 21 22 23 24 25 10 20 pF 5k
VOUT
MP7641
All resistors = 50 unless otherwise specified. Gain of all DACs set to 1 (no attenuation). NOTE: See Figure 12.
Figure 13. PSRR
5 pF 1k Test Load 27 28 3 4 12 13 16 17 26 1 2 5 11 14 15 18 19 20 21 22 23 24 25 10
VR0 VO0 VR1 VO1 VR2 VO2 VR3 VO3 VR4 VO4 VR5 VO5 VR6 VO6 VR7 VO7 N/C SDI SDO CLK LD RST N/C
20 pF
5k
VOUT
9
DGND AGND
MP7641
1.6 Vp-p
All resistors = 50 unless otherwise specified. NOTE: See Graph 16.
Figure 14. Frequency Response / THD Response
Rev. 2.00 15
MP7641
PERFORMANCE CHARACTERISTICS Channel-to-Channel Crosstalk (Gain vs. Frequency; All DACs set to full scale; VREF=1.6 Vp-p)
Output DACs shown below are: DAC 1, 7, 2, 6, 5, 3 & 4. Output DACs shown below are: DAC 2, 0, 7, 6, 4, 3 & 5.
dB
DAC 1
dB
DAC 2
DAC 0 Driven
MHz
DAC 1 Driven
MHz
Graph 1.
Graph 2.
Output DACs shown below are: DAC 1, 3, 7, 4, 0, 5 & 6. dB
DAC 1
Output DACs shown below are: DAC 2, 4, 1, 5, 0, 6 & 7. dB
DAC 2
DAC 2 Driven
MHz
DAC 3 Driven
MHz
Graph 3.
Graph 4.
Output DACs shown below are: DAC 5, 3, 6, 2, 7, 0 & 1. dB
DAC 5
Output DACs shown below are: DAC 4, 6, 3, 2, 1, 0 & 7. dB
DAC 4
DAC 4 Driven
MHz
DAC 5 Driven
MHz
Graph 5.
Graph 6.
Output DACs shown below are: DAC 7, 5, 0, 4, 3, 1 & 2. dB
DAC 7
Output DACs shown below are: DAC 6, 0, 5, 4, 1, 2 & 3. dB
DAC 6
DAC 6 Driven
MHz
DAC 7 Driven
MHz
Graph 7.
Rev. 2.00 16
Graph 8.
MP7641
Digital Input Code
Digital Input Code
Graph 9. Linearity Error vs. Digital Input Code DACs 0 to 3
Graph 10. Linearity Error vs. Digital Input Code DACs 4 to 7
Graph 11. Reset Voltage vs. Temperature
Graph 12. PSRR vs. Frequency
VR = 500 mV p-p
Gain
Phase
VR = 1.6 V p-p
Graph 13. Gain & Phase vs. Frequency
Rev. 2.00 17
Graph 14. Feedthrough vs. Frequency
MP7641
VR = 6 V p-p 3 V p-p
1.5 V p-p 1 V p-p 0.5 V p-p
Graph 15. Gain (VO/VR) vs. Frequency Open Loop/Unloaded Output*
Graph 16. THD vs. Frequency
Graph 17. ICC vs. Temperature
Graph 18. IEE vs. Temperature
A GE = +1.5% FSR
VRR Positive
All DACs driven, measured DAC @ zero scale and other DACs @ full scale B
VRR Negative
All DACs except monitored driven, all DACs @ full scale
-V
Graph 19. Reference Input Voltage Range vs. Supply Voltages
* A 2K or 5K resistor across output and VEE will remove peaking (see Graph 26).
Graph 20. All Channel Crosstalk vs. Frequency
Rev. 2.00 18
MP7641
LD (5 V/DIV) VR = 3 V Digital Code = 2550255 VO (2 V/DIV) VR (2 V/DIV)
Digital Code = All Ones
VO (2 V/DIV)
2s/DIV
2s/DIV
Graph 21. Digital Settling
Graph 22. Pulse Response (tR = tF = 100 ns for VR)
VR (2 V/DIV)
LD (5 V/DIV)
VO (2 V/DIV)
VO (10mV/DIV)
2s/DIV
2s/DIV
Graph 23. 128 kHz Sawtooth Waveform Response
Graph 24. Clock and SDI Feedthrough
LD (5 V/DIV)
Gain (5 dB/DIV)
VO (10mV/DIV)
Group Delay (20 ns/DIV)
2s/DIV
MHz
Graph 25. Clock/SDI Feedthrough
Graph 26. Typical Gain and Group Delay vs. Frequency (with 5K resistor across output to VEE)
Rev. 2.00 19
MP7641
28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) NN28
S
28 1 Q1 D
15 14 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN 0.130 0.015 0.014 0.038 0.008 1.340 0.290 0.240 MAX 0.230 -- 0.023 0.065 0.015 1.485 0.325 0.310
MILLIMETERS MIN 3.30 0.381 0.356 0.965 0.203 34.04 7.37 6.10 MAX 5.84 -- 0.584 1.65 0.381 37.72 8.26 7.87
0.100 BSC 0.115 0 0.055 0.020 (1) 0.150 15 0.070 0.100
2.54 BSC 2.92 0 1.40 0.508 3.81 15 1.78 2.54
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 20
MP7641
28 LEAD SMALL OUTLINE (335 MIL EIAJ SOIC) R28
D
28
15
E
1 14
H
C Seating Plane e B A1 L A
MILLIMETERS SYMBOL A A1 B C D E e H L MIN 2.60 MAX 2.80
INCHES MIN 0.102 MAX 0.110
0.2 (typ.) 0.3 0.10 17.6 8.3 0.5 0.20 18.0 8.5
0.008 (typ.) 0.012 0.004 0.693 0.327 0.020 0.008 0.709 0.335
1.27 (typ.) 11.5 0.8 12.1 1.2
0.050 (typ.) 0.453 0.031 0.477 0.047
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MP7641 Notes
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MP7641 Notes
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MP7641
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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